C8051F02X Datasheet, PDF (109/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
12.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The
SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs
found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the
sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with the
MCS-51™ instruction set. Table 12.2 lists the SFRs implemented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to
0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.) are bit-addressable as well as
byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for
future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding
pages of the datasheet, as indicated in Table 12.3, for a detailed description of each register.
Table 12.2. Special Function Register (SFR) Memory Map
F8 SPI0CN PCA0H PCA0CPH0 PCA0CPH1 PCA0CPH2 PCA0CPH3 PCA0CPH4 WDTCN
F0
B
SCON1 SBUF1 SADDR1
TL4
TH4
EIP1
EIP2
E8 ADC0CN PCA0L PCA0CPL0 PCA0CPL1 PCA0CPL2 PCA0CPL3 PCA0CPL4 RSTSRC
E0 ACC
XBR0
XBR1
XBR2 RCAP4L RCAP4H EIE1
EIE2
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4
D0
PSW
REF0CN DAC0L DAC0H DAC0CN DAC1L DAC1H DAC1CN
C8 T2CON T4CON RCAP2L RCAP2H
TL2
TH2
SMB0CR
C0 SMB0CN SMB0STA SMB0DAT SMB0ADR ADC0GTL ADC0GTH ADC0LTL ADC0LTH
B8
IP
SADEN0 AMX0CF AMX0SL ADC0CF P1MDIN ADC0L ADC0H
B0
P3
OSCXCN OSCICN
P74OUT† FLSCL FLACL
A8
IE
SADDR0 ADC1CN ADC1CF AMX1SL
P3IF
SADEN1 EMI0CN
A0
P2
EMI0TC
EMI0CF P0MDOUT P1MDOUT P2MDOUT P3MDOUT
98 SCON0 SBUF0 SPI0CFG SPI0DAT ADC1 SPI0CKR CPT0CN CPT1CN
90
P1
TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H
P7†
88 TCON
TMOD
TL0
TL1
TH0
TH1
CKCON PSCTL
80
P0
SP
DPL
DPH
P4†
P5†
P6†
PCON
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
(bit addressable)
Table 12.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address Description
ACC
0xE0
Accumulator
ADC0CF
0xBC
ADC0 Configuration
ADC0CN
0xE8
ADC0 Control
ADC0GTH
0xC5
ADC0 Greater-Than High
ADC0GTL
0xC4
ADC0 Greater-Than Low
ADC0H
0xBF
ADC0 Data Word High
ADC0L
0xBE
ADC0 Data Word Low
Rev. 1.4
Page No.
page 115
page 49*, page 65**
page 50*, page 66**
page 53*, page 69**
page 53*, page 69**
page 51*, page 67**
page 51*, page 67**
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