C8051F02X Datasheet, PDF (132/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 13.4. RSTSRC: Reset Source Register
R
R/W
R/W
R/W
R
R
R/W
R
Reset Value
- CNVRSEF C0RSEF SWRSEF WDTRSF MCDRSF PORSF PINRSF Variable
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xEF
(Note: Do not use read-modify-write operations on this register.)
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Reserved.
CNVRSEF: Convert Start Reset Source Enable and Flag
Write: 0: CNVSTR is not a reset source.
1: CNVSTR is a reset source (active low).
Read: 0: Source of prior reset was not CNVSTR.
1: Source of prior reset was CNVSTR.
C0RSEF: Comparator0 Reset Enable and Flag
Write: 0: Comparator0 is not a reset source.
1: Comparator0 is a reset source (active low).
Read: 0: Source of prior reset was not Comparator0.
1: Source of prior reset was Comparator0.
SWRSF: Software Reset Force and Flag
Write: 0: No Effect.
1: Forces an internal reset. /RST pin is not affected.
Read: 0: Prior reset source was not a write to the SWRSF bit.
1: Prior reset source was a write to the SWRSF bit.
WDTRSF: Watchdog Timer Reset Flag
0: Source of prior reset was not WDT timeout.
1: Source of prior reset was WDT timeout.
MCDRSF: Missing Clock Detector Flag
0: Source of prior reset was not Missing Clock Detector timeout.
1: Source of prior reset was Missing Clock Detector timeout.
PORSF: Power-On Reset Force and Flag
Write: 0: No effect.
1: Forces a Power-On Reset. /RST is driven low.
Read: 0: Source of prior reset was not POR.
1: Source of prior reset was POR.
PINRSF: HW Pin Reset Flag
0: Source of prior reset was not /RST pin.
1: Source of prior reset was /RST pin.
132
Rev. 1.4