C8051F02X Datasheet, PDF (183/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
18. SYSTEM MANAGEMENT BUS / I²C BUS (SMBUS0)
The SMBus0 I/O interface is a two-wire, bi-directional serial bus. SMBus0 is compliant with the System Manage-
ment Bus Specification, version 1.1, and compatible with the I²C serial bus. Reads and writes to the interface by the
system controller are byte oriented with the SMBus0 interface autonomously controlling the serial transfer of the
data. Data can be transferred at up to 1/8th of the system clock if desired (this can be faster than allowed by the
SMBus specification, depending on the system clock used). A method of extending the clock-low duration is avail-
able to accommodate devices with different speed capabilities on the same bus.
SMBus0 may operate as a master and/or slave, and may function on a bus with multiple masters. SMBus0 provides
control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP
control and generation. SMBus0 is controlled by SFRs as described in Section 18.4 on page 189.
Figure 18.1. SMBus0 Block Diagram
SFR Bus
SMB0CN
BESSSAFT
UNT T I ATO
SSAO
EE
YM
B
SMB0STA
SSSSSSSS
TTTTTTTT
AAAAAAAA
76543210
SMB0CR
CCCCCCCC
RRRRRRRR
76543210
Clock Divide
Logic
SYSCLK
SMBUS
IRQ
Interrupt
Request
SMBUS CONTROL LOGIC
Arbitration
SCL Synchronization
Status Generation
SCL Generation (Master Mode)
IRQ Generation
Data Path
Control
SCL
Control
SDA
Control
BA
BA
0000000b
7 MSBs
8
7
SMB0DAT
76543210
SSSSSSS
LLLLLLL
V V V V V V VG
6 5 4 3 2 1 0C
SMB0ADR
8
Read
SMB0DAT
8
1
0
Write to
SMB0DAT
FILTER
SCL
N
C
R
O
S
S
B
A
R
FILTER
SDA
N
SFR Bus
Port I/O
Rev. 1.4
183