C8051F02X Datasheet, PDF (131/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 13.3. WDTCN: Watchdog Timer Control Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
xxxxx111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xFF
Bits7-0:
Bit4:
Bits2-0:
WDT Control
Writing 0xA5 both enables and reloads the WDT.
Writing 0xDE followed within 4 system clocks by 0xAD disables the WDT.
Writing 0xFF locks out the disable feature.
Watchdog Status Bit (when Read)
Reading the WDTCN.[4] bit indicates the Watchdog Timer Status.
0: WDT is inactive
1: WDT is active
Watchdog Timeout Interval Bits
The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits, WDTCN.7 must
be set to 0.
Rev. 1.4
131