C8051F02X Datasheet, PDF (249/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
23. PROGRAMMABLE COUNTER ARRAY
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU interven-
tion than the standard 8051 counter/timers. PCA0 consists of a dedicated 16-bit counter/timer and five 16-bit capture/
compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the
Crossbar to Port I/O when enabled (See Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder” on
page 163). The counter/timer is driven by a programmable timebase that can select between six inputs as its source:
system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source
divided by 8, Timer 0 overflow, or an external clock signal on the ECI line. Each capture/compare module may be
configured to operate independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Out-
put, Frequency Output, 8-Bit PWM, or 16-Bit PWM (each is described in Section 23.2). The PCA is configured and
controlled through the system controller's Special Function Registers. The basic PCA block diagram is shown in
Figure 23.1.
Figure 23.1. PCA Block Diagram
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
PCA
CLOCK
MUX
16-Bit Counter/Timer
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4
Crossbar
Port I/O
Rev. 1.4
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