C8051F02X Datasheet, PDF (180/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 17.21. P4: Port4 Data Register
R/W
P4.7
Bit7
R/W
P4.6
Bit6
R/W
P4.5
Bit5
R/W
P4.4
Bit4
R/W
P4.3
Bit3
R/W
P4.2
Bit2
R/W
P4.1
Bit1
R/W
P4.0
Bit0
Reset Value
11111111
SFR Address:
0x84
Bits7-0:
P4.[7:0]: Port4 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20.
Read - Returns states of I/O pins.
0: P4.n pin is logic low.
1: P4.n pin is logic high.
Note: P4.7 (/WR), P4.6 (/RD), and P4.5 (ALE) can be driven by the External Data Memory Interface.
See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM” on
page 145 for more information.
Figure 17.22. P5: Port5 Data Register
R/W
P5.7
Bit7
R/W
P5.6
Bit6
R/W
P5.5
Bit5
R/W
P5.4
Bit4
R/W
P5.3
Bit3
R/W
P5.2
Bit2
R/W
P5.1
Bit1
R/W
P5.0
Bit0
Reset Value
11111111
SFR Address:
0x85
Bits7-0:
P5.[7:0]: Port5 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P74OUT bit = 0). See Figure 17.20.
Read - Returns states of I/O pins.
0: P5.n pin is logic low.
1: P5.n pin is logic high.
Note:
P5.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-multiplexed
mode). See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM”
on page 145 for more information about the External Memory Interface.
180
Rev. 1.4