C8051F02X Datasheet, PDF (270/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 24.4. FLASHADR: JTAG Flash Address Register
Bit15
Reset Value
0x0000
Bit0
This register holds the address for all JTAG Flash read, write, and erase operations. This register autoincrements
after each read or write, regardless of whether the operation succeeded or failed.
Bits15-0: Flash Operation 16-bit Address.
Figure 24.5. FLASHDAT: JTAG Flash Data Register
Reset Value
0000000000
Bit9
Bit0
This register is used to read or write data to the Flash memory across the JTAG interface.
Bits9-2:
Bit1:
Bit0:
DATA7-0: Flash Data Byte.
FAIL: Flash Fail Bit.
0: Previous Flash memory operation was successful.
1: Previous Flash memory operation failed. Usually indicates the associated memory location
was locked.
BUSY: Flash Busy Bit.
0: Flash interface logic is not busy.
1: Flash interface logic is processing a request. Reads or writes while BUSY = 1 will not
initiate another operation
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Rev. 1.4