C8051F02X Datasheet, PDF (192/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
18.4.2. Clock Rate Register
Figure 18.9. SMB0CR: SMBus0 Clock Rate Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xCF
Bits7-0:
SMB0CR.[7:0]: SMBus0 Clock Rate Preset
The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master mode. The
8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer. The timer counts up, and
when it rolls over to 0x00, the SCL logic state toggles.
The SMB0CR setting should be bounded by the following equation , where SMB0CR is the unsigned
8-bit value in register SMB0CR, and SYSCLK is the system clock frequency in Hz:
SMB0CR < ((288 – 0.85 ⋅ SYSCLK ) ⁄ 1.125 )
The resulting SCL signal high and low times are given by the following equations:
T_LOW = (256 – SMB0CR) ⁄ SYSCLK
T_HIGH ≅ (258 – SMB0CR) ⁄ SYSCLK + 625ns
Using the same value of SMB0CR from above, the Bus Free Timeout period is given in the following
equation:
T_BFT
≅
10
×
(_{---2---5---6----–-----}S_---M_------B_----0---C_----R_----)_----+-----1-
SYSCLK
192
Rev. 1.4