C8051F02X Datasheet, PDF (162/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
The C8051F020/1/2/3 devices have a wide array of digital resources which are available through the four lower I/O
Ports: P0, P1, P2, and P3. Each of the pins on P0, P1, P2, and P3, can be defined as a General-Purpose I/O (GPIO) pin
or can be controlled by a digital peripheral or function (like UART0 or /INT1 for example), as shown in Figure 17.2.
The system designer controls which digital functions are assigned pins, limited only by the number of pins available.
This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of
a Port I/O pin can always be read from its associated Data register regardless of whether that pin has been assigned to
a digital peripheral or behaves as GPIO. The Port pins on Port 1 can be used as Analog Inputs to ADC1.
An External Memory Interface which is active during the execution of a MOVX instruction whose target address
resides in off-chip memory can be active on either the lower Ports or the upper Ports. See Section “16. EXTERNAL
DATA MEMORY INTERFACE AND ON-CHIP XRAM” on page 145 for more information about the External
Memory Interface.
The upper Ports (available on C8051F020/2) can be byte-accessed as GPIO pins.
Figure 17.2. Lower Port I/O Functional Block Diagram
Highest
Priority
UART0
2
4
SPI
2
SMBus
2
UART1
6
PCA
Comptr.
2
Outputs
T0, T1,
T2, T2EX,
8
T4,T4EX
/INT0,
/INT1
Lowest
Priority
Port
Latches
/SYSCLK
CNVSTR
8
P0 _(P0.0-P0.7)
8
P1 _(P1.0-P1.7)
8
P2 _(P2.0-P2.7)
8
P3 _(P3.0-P3.7)
XBR0, XBR1,
XBR2, P1MDIN
Registers
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Registers
Priority
Decoder
8
Digital
Crossbar
8
P0
I/O
Cells
P1
I/O
Cells
External
Pins
P0.0
P0.7
Highest
Priority
P1.0
P1.7
8
P2
I/O
Cells
P2.0
P2.7
8
P3
I/O
Cells
P3.0
P3.7
Lowest
Priority
To External
Memory
Interface
(EMIF)
To
ADC1
Input
162
Rev. 1.4