C8051F02X Datasheet, PDF (147/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 16.1. EMI0CN: External Memory Interface Control
R/W
PGSEL7
Bit7
R/W
PGSEL6
Bit6
R/W
PGSEL5
Bit5
R/W
PGSEL4
Bit4
R/W
PGSEL3
Bit3
R/W
PGSEL2
Bit2
R/W
PGSEL1
Bit1
R/W
PGSEL0
Bit0
Reset Value
00000000
SFR Address:
0xAF
Bits7-0:
PGSEL[7:0]: XRAM Page Select Bits.
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when
using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM.
0x00: 0x0000 to 0x00FF
0x01: 0x0100 to 0x01FF
...
0xFE: 0xFE00 to 0xFEFF
0xFF: 0xFF00 to 0xFFFF
Figure 16.2. EMI0CF: External Memory Configuration
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
PRTSEL EMD2 EMD1 EMD0 EALE1 EALE0 00000011
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xA3
Bits7-6:
Bit5:
Bit4:
Bits3-2:
Bits1-0:
Unused. Read = 00b. Write = don’t care.
PRTSEL: EMIF Port Select.
0: EMIF active on P0-P3.
1: EMIF active on P4-P7.
EMD2: EMIF Multiplex Mode Select.
0: EMIF operates in multiplexed address/data mode.
1: EMIF operates in non-multiplexed mode (separate address and data pins).
EMD1-0: EMIF Operating Mode Select.
These bits control the operating mode of the External Memory Interface.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to on-chip
memory space.
01: Split Mode without Bank Select: Accesses below the 4k boundary are directed on-chip. Accesses
above the 4k boundary are directed off-chip. 8-bit off-chip MOVX operations use the current contents
of the Address High port latches to resolve upper address byte. Note that in order to access off-chip
space, EMI0CN must be set to a page that is not contained in the on-chip address space.
10: Split Mode with Bank Select: Accesses below the 4k boundary are directed on-chip. Accesses
above the 4k boundary are directed off-chip. 8-bit off-chip MOVX operations use the contents of
EMI0CN to determine the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to the CPU.
EALE1-0: ALE Pulse-Width Select Bits (only has effect when EMD2 = 0).
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
Rev. 1.4
147