C8051F02X Datasheet, PDF (29/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
1.8. 8-Bit Analog to Digital Converter
The C8051F020/1/2/3 has an on-board 8-bit SAR ADC (ADC1) with an 8-channel input multiplexer and programma-
ble gain amplifier. This ADC features a 500 ksps maximum throughput and true 8-bit accuracy with an INL of
±1LSB. Eight input pins are available for measurement. The ADC is under full control of the CIP-51 microcontroller
via the Special Function Registers. The ADC1 voltage reference is selected between the analog power supply (AV+)
and an external VREF pin. On C8051F020/2 devices, ADC1 has its own dedicated VREF1 input pin; on
C8051F021/3 devices, ADC1 shares the VREFA input pin with the 12/10-bit ADC0. User software may put ADC1
into shutdown mode to save power.
A programmable gain amplifier follows the analog multiplexer. The gain stage can be especially useful when differ-
ent ADC input channels have widely varied input voltage signals, or when it is necessary to "zoom in" on a signal
with a large DC offset (in differential mode, a DAC could be used to provide the DC offset). The PGA gain can be set
in software to 0.5, 1, 2, or 4.
A flexible conversion scheduling system allows ADC1 conversions to be initiated by software commands, timer
overflows, or an external input signal. ADC1 conversions may also be synchronized with ADC0 software-com-
manded conversions. Conversion completions are indicated by a status bit and an interrupt (if enabled), and the
resulting 8-bit data word is latched into an SFR upon completion.
Figure 1.12. 8-Bit ADC Diagram
Analog Multiplexer
Configuration, Control, and Data Registers
AIN1.0
AIN1.1
AIN1.2
AIN1.3
AIN1.4
AIN1.5
AIN1.6
AIN1.7
8-to-1
AMUX
Programmable Gain
Amplifier
AV+
X
+
-
8-Bit
SAR
8
ADC
External VREF
Pin
AV+
VREF Start Conversion
ADC Data
Register
Conversion
Complete
Interrupt
Write to AD1BUSY
Timer 3 Overflow
CNVSTR Input
Timer 2 Overflow
Write to AD0BUSY
(synchronized with
ADC0)
Rev. 1.4
29