C8051F02X Datasheet, PDF (86/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 8.4. DAC0CN: DAC0 Control Register
R/W
R/W
DAC0EN
-
Bit7
Bit6
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
- DAC0MD1 DAC0MD0 DAC0DF2 DAC0DF1 DAC0DF0 00000000
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xD4
Bit7:
Bits6-5:
Bits4-3:
Bits2-0:
DAC0EN: DAC0 Enable Bit.
0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode.
1: DAC0 Enabled. DAC0 Output pin is active; DAC0 is operational.
UNUSED. Read = 00b; Write = don’t care.
DAC0MD1-0: DAC0 Mode Bits.
00: DAC output updates occur on a write to DAC0H.
01: DAC output updates occur on Timer 3 overflow.
10: DAC output updates occur on Timer 4 overflow.
11: DAC output updates occur on Timer 2 overflow.
DAC0DF2-0: DAC0 Data Format Bits:
000: The most significant nibble of the DAC0 Data Word is in DAC0H[3:0], while the least
significant byte is in DAC0L.
DAC0H
DAC0L
MSB
LSB
001: The most significant 5-bits of the DAC0 Data Word is in DAC0H[4:0], while the least
significant 7-bits are in DAC0L[7:1].
DAC0H
DAC0L
MSB
LSB
010: The most significant 6-bits of the DAC0 Data Word is in DAC0H[5:0], while the least
significant 6-bits are in DAC0L[7:2].
DAC0H
DAC0L
MSB
LSB
011:
MSB
The most significant 7-bits of the DAC0 Data Word is in DAC0H[6:0], while the least
significant 5-bits are in DAC0L[7:3].
DAC0H
DAC0L
LSB
1xx: The most significant 8-bits of the DAC0 Data Word is in DAC0H[7:0], while the least
significant 4-bits are in DAC0L[7:4].
DAC0H
DAC0L
MSB
LSB
86
Rev. 1.4