C8051F02X Datasheet, PDF (127/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
13. RESET SOURCES
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state,
the following occur:
• CIP-51 halts program execution
• Special Function Registers (SFRs) are initialized to their defined reset values
• External port pins are forced to a known state
• Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data mem-
ory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is
reset, the stack is effectively lost even though the data on the stack are not altered.
The I/O port latches are reset to 0xFF (all logic 1’s), activating internal weak pull-ups which take the external I/O pins
to a high state. Note that weak pull-ups are disabled during the reset, and enabled when the device exits the reset state.
This allows power to be conserved while the part is held in reset. For VDD Monitor resets, the /RST pin is driven low
until the end of the VDD reset timeout.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator
running at 2 MHz. Refer to Section “14. OSCILLATORS” on page 135 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled using its longest timeout interval (see Section
“13.8. Watchdog Timer Reset” on page 129). Once the system clock source is stable, program execution begins at
location 0x0000.
There are seven sources for putting the MCU into the reset state: power-on/power-fail, external /RST pin, external
CNVSTR signal, software command, Comparator0, Missing Clock Detector, and Watchdog Timer. Each reset source
is described in the following sections.
Figure 13.1. Reset Sources
VDD
(Port
I/O)
CP0+
CP0-
XTAL1
XTAL2
Crossbar
CNVSTR
(CNVSTR
reset
enable)
Comparator0
+
-
(CP0
reset
enable)
Supply
Monitor
+
-
Supply
Reset
Timeout
Internal
Clock
Generator
OSC
Missing
Clock
Detector
(one-
shot)
EN
WDT
EN PRE
System
Clock
Clock Select
CIP-51
Software Reset
Microcontroller
Core
System Reset
Extended Interrupt
Handler
(wired-OR)
Reset
Funnel
/RST
Rev. 1.4
127