C8051F02X Datasheet, PDF (216/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
21.1. UART1 Operational Modes
UART1 provides four operating modes (one synchronous and three asynchronous) selected by setting configuration
bits in the SCON1 register. These four modes offer different baud rates and communication protocols. The four
modes are summarized in Table 21.1.
Mode
0
1
2
3
Synchronization
Synchronous
Asynchronous
Asynchronous
Asynchronous
Table 21.1. UART1 Modes
Baud Clock
SYSCLK / 12
Timer 1 or 4 Overflow
SYSCLK / 32 or SYSCLK / 64
Timer 1 or 4 Overflow
Data Bits
8
8
9
9
Start/Stop Bits
None
1 Start, 1 Stop
1 Start, 1 Stop
1 Start, 1 Stop
21.1.1. Mode 0: Synchronous Mode
Mode 0 provides synchronous, half-duplex communication. Serial data is transmitted and received on the RX1 pin.
The TX1 pin provides the shift clock for both transmit and receive. The MCU must be the master since it generates
the shift clock for transmission in both directions (see the interconnect diagram in Figure 21.2).
Data transmission begins when an instruction writes a data byte to the SBUF1 register. Eight data bits are transferred
LSB first (see the timing diagram in Figure 21.3), and the TI1 Transmit Interrupt Flag (SCON1.1) is set at the end of
the eighth bit time. Data reception begins when the REN1 Receive Enable bit (SCON1.4) is set to logic 1 and the RI1
Receive Interrupt Flag (SCON1.0) is cleared. One cycle after the eighth bit is shifted in, the RI1 flag is set and recep-
tion stops until software clears the RI1 bit. An interrupt will occur if enabled when either TI1 or RI1 are set.
The Mode 0 baud rate is SYSCLK / 12. RX1 is forced to open-drain in Mode 0, and an external pull-up will typically
be required.
Figure 21.2. UART1 Mode 0 Interconnect
TX
C8051Fxxx
RX
CLK
DATA
Shift
Reg.
8 Extra Outputs
Figure 21.3. UART1 Mode 0 Timing Diagram
RX (data out)
TX (clk out)
MODE 0 TRANSMIT
D0
D1
D2
D3
D4
D5
D6
D7
RX (data in)
TX (clk out)
MODE 0 RECEIVE
D0
D1
D2
D3
D4
D5
D6
D7
216
Rev. 1.4