C8051F02X Datasheet, PDF (47/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1
Figure 5.5. AMX0CF: AMUX0 Configuration Register (C8051F020/1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
-
-
AIN67IC AIN45IC AIN23IC AIN01IC 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xBA
Bits7-4:
Bit3:
Bit2:
Bit1:
Bit0:
UNUSED. Read = 0000b; Write = don’t care
AIN67IC: AIN6, AIN7 Input Pair Configuration Bit
0: AIN6 and AIN7 are independent single-ended inputs
1: AIN6, AIN7 are (respectively) +, - differential input pair
AIN45IC: AIN4, AIN5 Input Pair Configuration Bit
0: AIN4 and AIN5 are independent single-ended inputs
1: AIN4, AIN5 are (respectively) +, - differential input pair
AIN23IC: AIN2, AIN3 Input Pair Configuration Bit
0: AIN2 and AIN3 are independent single-ended inputs
1: AIN2, AIN3 are (respectively) +, - differential input pair
AIN01IC: AIN0, AIN1 Input Pair Configuration Bit
0: AIN0 and AIN1 are independent single-ended inputs
1: AIN0, AIN1 are (respectively) +, - differential input pair
NOTE: The ADC0 Data Word is in 2’s complement format for channels configured as differential.
Rev. 1.4
47