C8051F02X Datasheet, PDF (259/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
23.3. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of PCA0.
Figure 23.10. PCA0CN: PCA Control Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
CF
CR
-
CCF4
CCF3
CCF2
CCF1
CCF0 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
(bit addressable) 0xD8
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000. When the
Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector to the CF
interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by
software. See “Important Note About the PCA0CN Register” on page 251.
CR: PCA0 Counter/Timer Run Control.
This bit enables/disables the PCA0 Counter/Timer.
0: PCA0 Counter/Timer disabled.
1: PCA0 Counter/Timer enabled.
UNUSED. Read = 0b, Write = don't care.
CCF4: PCA0 Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
CCF3: PCA0 Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
CCF2: PCA0 Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
CCF1: PCA0 Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
CCF0: PCA0 Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.
Rev. 1.4
259