C8051F02X Datasheet, PDF (175/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 17.14. P1MDOUT: Port1 Output Mode Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xA5
Bits7-0: P1MDOUT.[7:0]: Port1 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
Note:
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always
configured as Open-Drain when they appear on Port pins.
Figure 17.15. P2: Port2 Data Register
R/W
P2.7
Bit7
R/W
P2.6
Bit6
R/W
P2.5
Bit5
R/W
P2.4
Bit4
R/W
P2.3
Bit3
R/W
P2.2
Bit2
R/W
P2.1
Bit1
R/W
Reset Value
P2.0 11111111
Bit0 SFR Address:
(bit addressable) 0xA0
Bits7-0:
P2.[7:0]: Port2 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P2MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).
0: P2.n pin is logic low.
1: P2.n pin is logic high.
Note:
P2.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multiplexed
mode, or as Address[7:0] in Non-multiplexed mode). See Section “16. EXTERNAL DATA MEM-
ORY INTERFACE AND ON-CHIP XRAM” on page 145 for more information about the External
Memory Interface.
Figure 17.16. P2MDOUT: Port2 Output Mode Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xA6
Bits7-0: P2MDOUT.[7:0]: Port2 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
Note:
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always
configured as Open-Drain when they appear on Port pins.
Rev. 1.4
175