C8051F02X Datasheet, PDF (211/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
20.3. Frame and Transmission Error Detection
Frame error detection is available in the following modes when the SSTAT0 bit in register PCON is set to logic 1.
Note: The SSTAT0 bit must be logic 1 to access any of the status bits (FE0, RXOVR0, and TXCOL0). To access the
UART0 Mode Select bits (SM00, SM10, and SM20), the SSTAT0 bit must be logic 0.
All Modes:
The Transmit Collision bit (TXCOL0 bit in register SCON0) reads ‘1’ if user software writes data to the SBUF0 reg-
ister while a transmit is in progress. Note that the TXCOL0 bit also functions as the SM20 bit when the SSTAT0 bit in
register PCON is logic 0.
Modes 1, 2, and 3:
The Receive Overrun bit (RXOVR0 in register SCON0) reads ‘1’ if a new data byte is latched into the receive buffer
before software has read the previous byte. Note that the RXOVR0 bit also functions as the SM10 bit when the
SSTAT0 bit in register PCON is logic 0.
The Frame Error bit (FE0 in register SCON0) reads ‘1’ if an invalid (low) STOP bit is detected. Note that the FE0 bit
also functions as the SM00 bit when the SSTAT0 bit in register PCON is logic 0.
Rev. 1.4
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