C8051F02X Datasheet, PDF (213/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 20.8. SCON0: UART0 Control Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SM00/FE0 SM10/RXOV0 SM20/TXCOL0 REN0 TB80 RB80 TI0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
R/W Reset Value
RI0 00000000
Bit0 SFR Address:
0x98
Bits7-6:
The function of these bits is determined by the SSTAT0 bit in register PCON.
If SSTAT0 is logic 1, these bits are UART0 status indicators as described in Section 20.3.
If SSTAT0 is logic 0, these bits select the Serial Port Operation Mode as shown below.
SM00-SM10: Serial Port Operation Mode:
SM00
0
0
1
1
SM10
0
1
0
1
Mode
Mode 0: Synchronous Mode
Mode 1: 8-Bit UART, Variable Baud Rate
Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 3: 9-Bit UART, Variable Baud Rate
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SM20: Multiprocessor Communication Enable.
If SSTAT0 is logic 1, this bit is a UART0 status indicator as described in Section 20.3.
If SSTAT0 is logic 0, the function of this bit is dependent on the Serial Port Operation Mode.
Mode 0: No effect.
Mode 1: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
Modes 2 and 3: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1 and the received
address matches the UART0 address or the broadcast address.
REN0: Receive Enable.
This bit enables/disables the UART0 receiver.
0: UART0 reception disabled.
1: UART0 reception enabled.
TB80: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in Modes 2 and 3. It is not used
in Modes 0 and 1. Set or cleared by software as required.
RB80: Ninth Receive Bit.
The bit is assigned the logic level of the ninth bit received in Modes 2 and 3. In Mode 1, if SM20 is
logic 0, RB80 is assigned the logic level of the received stop bit. RB8 is not used in Mode 0.
TI0: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in Mode 0, or
at the beginning of the stop bit in other modes). When the UART0 interrupt is enabled, setting this bit
causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually
by software
RI0: Receive Interrupt Flag.
Set by hardware when a byte of data has been received by UART0 (as selected by the SM20 bit).
When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 inter-
rupt service routine. This bit must be cleared manually by software.
Rev. 1.4
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