C8051F02X Datasheet, PDF (199/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
19.2. SPI0 Operation
Only a SPI master device can initiate a data transfer. SPI0 is placed in master mode by setting the Master Enable flag
(MSTEN, SPI0CN.1). Writing a byte of data to the SPI0 data register (SPI0DAT) when in Master Mode starts a data
transfer. The SPI0 master immediately shifts out the data serially on the MOSI line while providing the serial clock
on SCK. The SPIF (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are enabled, an interrupt
request is generated when the SPIF flag is set. The SPI0 master can be configured to shift in/out from one to eight bits
in a transfer operation in order to accommodate slave devices with different word lengths. The SPIFRS bits in the
SP0I Configuration Register (SPI0CFG.[2:0]) are used to select the number of bits to shift in/out in a transfer opera-
tion.
While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device simultaneously
transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex operation. The data byte
received from the slave replaces the data in the master's data register. Therefore, the SPIF flag serves as both a trans-
mit-complete and receive-data-ready flag. The data transfer in both directions is synchronized with the serial clock
generated by the master. Figure 19.3 illustrates the full-duplex operation of an SPI master and an addressed slave.
Figure 19.3. Full Duplex Operation
MASTER DEVICE
MOSI
MOSI
SLAVE DEVICE
SPI SHIFT REGISTER
76543210
Receive Buffer
MISO
NSS
VDD
MISO
NSS
SPI SHIFT REGISTER
76543210
Receive Buffer
Baud Rate
SCK
SCK
Generator
Px.y
When SPI0 is enabled and not configured as a master, it will operate as an SPI slave. Another SPI device acting as a
master will initiate a transfer by driving the NSS input signal low. The master then shifts data out of the shift register
on the MOSI pin using the its serial clock. The SPIF flag is set to logic 1 when the NSS signal goes high, indicating
the end of a data transfer. Note that following a rising edge on NSS, the receive buffer will always contain the last
8 bits of data in the slave shift register. The slave can load its shift register for the next data transfer by writing to the
SPI0 data register. The slave must make the write to the data register at least one SPI serial clock cycle before the
master starts the next transmission. Otherwise, the byte of data already in the slave's shift register will be transferred.
Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte
transfer.
The SPI0 data register is double buffered on reads, but not on writes. If a write to SPI0DAT is attempted during a data
transfer, the WCOL flag (SPI0CN.6) will be set to logic 1 and the write will be ignored. The current data transfer will
continue uninterrupted. A read of the SPI0 data register by the system controller actually reads the receive buffer. The
receive overrun flag (RXOVRN in register SPI0CN) is set anytime a SPI0 slave detects a rising edge on NSS while
the receive buffer still holds unread data from a previous transfer. The new data is not transferred to the receive
buffer, allowing the previously received data byte to be read. The data byte causing the overrun is lost.
Rev. 1.4
199