C8051F02X Datasheet, PDF (114/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 12.6. PSW: Program Status Word
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Reset Value
CY
AC
F0
RS1
RS0
OV
F1
PARITY 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
(bit addressable) 0xD0
Bit7:
Bit6:
Bit5:
Bits4-3:
CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtrac-
tion). It is cleared to 0 by all other arithmetic operations.
AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from
(subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations.
F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
RS1-RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
RS1
RS0 Register Bank
Address
0
0
0
0x00 - 0x07
0
1
1
0x08 - 0x0F
1
0
2
0x10 - 0x17
1
1
3
0x18 - 0x1F
Bit2:
Bit1:
Bit0:
OV: Overflow Flag.
This bit is set to 1 if the last arithmetic operation resulted in a carry (addition), borrow (subtraction),
or overflow (multiply or divide). It is cleared to 0 by all other arithmetic operations.
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag.
This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even.
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Rev. 1.4