C8051F02X Datasheet, PDF (214/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 20.9. SBUF0: UART0 Data Buffer Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0x99
Bits7-0:
SBUF0.[7:0]: UART0 Buffer Bits 7-0 (MSB-LSB)
This SFR accesses two registers; a transmit shift register and a receive latch register. When data is
written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a
byte to SBUF0 is what initiates the transmission. A read of SBUF0 returns the contents of the receive
latch.
Figure 20.10. SADDR0: UART0 Slave Address Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xA9
Bits7-0:
SADDR0.[7:0]: UART0 Slave Address
The contents of this register are used to define the UART0 slave address. Register SADEN0 is a bit
mask to determine which bits of SADDR0 are checked against a received address: corresponding bits
set to logic 1 in SADEN0 are checked; corresponding bits set to logic 0 are “don’t cares”.
Figure 20.11. SADEN0: UART0 Slave Address Enable Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xB9
Bits7-0:
SADEN0.[7:0]: UART0 Slave Address Enable
Bits in this register enable corresponding bits in register SADDR0 to determine the UART0 slave
address.
0: Corresponding bit in SADDR0 is a “don’t care”.
1: Corresponding bit in SADDR0 is checked against a received address.
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Rev. 1.4