C8051F02X Datasheet, PDF (59/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F022/3
6. ADC0 (10-BIT ADC, C8051F022/3 ONLY)
The ADC0 subsystem for the C8051F022/3 consists of a 9-channel, configurable analog multiplexer (AMUX0), a
programmable gain amplifier (PGA0), and a 100 ksps, 10-bit successive-approximation-register ADC with integrated
track-and-hold and Programmable Window Detector (see block diagram in Figure 6.1). The AMUX0, PGA0, Data
Conversion Modes, and Window Detector are all configurable under software control via the Special Function Regis-
ters shown in Figure 6.1. The voltage reference used by ADC0 is selected as described in Section “9. VOLTAGE
REFERENCE (C8051F020/2)” on page 91 for C8051F020/2 devices, or Section “10. VOLTAGE REFERENCE
(C8051F021/3)” on page 93 for C8051F021/3 devices. The ADC0 subsystem (ADC0, track-and-hold and PGA0) is
enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is
in low power shutdown when this bit is logic 0.
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Figure 6.1. 10-Bit ADC0 Functional Block Diagram
ADC0GTH
ADC0GTL
ADC0LTH
ADC0LTL
20
+
-
+
- 9-to-1
+ ^AMUX
(SE or
- ^DIFF)
+
-
AD0EN
AV+
X
+
-
AGND
AV+
10-Bit
SAR
10
ADC
Comb.
Logic
10
AD0WINT
TEMP
SENSOR
AGND
00
Start Conversion ⁰¹
10
11
AD0BUSY (W)
Timer 3 Overflow
CNVSTR
Timer 2 Overflow
AMX0CF
AMX0SL
ADC0CF
ADC0CN
6.1. Analog Multiplexer and PGA
Eight of the AMUX channels are available for external measurements while the ninth channel is internally connected
to an on-chip temperature sensor (temperature transfer function is shown in Figure 6.2). AMUX input pairs can be
programmed to operate in either differential or single-ended mode. This allows the user to select the best measure-
ment technique for each input channel, and even accommodates mode changes "on-the-fly". The AMUX defaults to
all single-ended inputs upon reset. There are two registers associated with the AMUX: the Channel Selection register
AMX0SL (Figure 6.6), and the Configuration register AMX0CF (Figure 6.7). The table in Figure 6.6 shows AMUX
functionality by channel, for each possible configuration. The PGA amplifies the AMUX output signal by an amount
determined by the states of the AMP0GN2-0 bits in the ADC0 Configuration register, ADC0CF (Figure 6.7). The
PGA can be software-programmed for gains of 0.5, 2, 4, 8 or 16. Gain defaults to unity on reset.
Rev. 1.4
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