C8051F02X Datasheet, PDF (65/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F022/3
Figure 6.7. ADC0CF: ADC0 Configuration Register (C8051F022/3)
R/W
AD0SC4
Bit7
R/W
AD0SC3
Bit6
R/W
AD0SC2
Bit5
R/W
AD0SC1
Bit4
R/W
AD0SC0
Bit3
R/W
R/W
R/W
Reset Value
AMP0GN2 AMP0GN1 AMP0GN0 11111000
Bit2
Bit1
Bit0 SFR Address:
0xBC
Bits7-3:
AD0SC4-0: ADC0 SAR Conversion Clock Period Bits
SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers
to the 5-bit value held in AD0SC4-0, and CLK_SAR0 refers to the desired ADC0 SAR clock. See
Table 6.1 on page 74 for SAR clock setting requirements.
AD0SC = -^S---^Y----^S---^C-----^L---^K--- – 1
CLK_SAR0
Bits2-0:
AMP0GN2-0: ADC0 Internal Amplifier Gain (PGA)
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5
Rev. 1.4
65