C8051F02X Datasheet, PDF (179/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 17.20. P74OUT: Ports 7 - 4 Output Mode Register
R/W
P7H
Bit7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
P7L
P6H
P6L
P5H
P5L
P4H
P4L 00000000
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xB5
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
P7H: Port7 Output Mode High Nibble Bit.
0: P7.[7:4] configured as Open-Drain.
1: P7.[7:4] configured as Push-Pull.
P7L: Port7 Output Mode Low Nibble Bit.
0: P7.[3:0] configured as Open-Drain.
1: P7.[3:0] configured as Push-Pull.
P6H: Port6 Output Mode High Nibble Bit.
0: P6.[7:4] configured as Open-Drain.
1: P6.[7:4] configured as Push-Pull.
P6L: Port6 Output Mode Low Nibble Bit.
0: P6.[3:0] configured as Open-Drain.
1: P6.[3:0] configured as Push-Pull.
P5H: Port5 Output Mode High Nibble Bit.
0: P5.[7:4] configured as Open-Drain.
1: P5.[7:4] configured as Push-Pull.
P5L: Port5 Output Mode Low Nibble Bit.
0: P5.[3:0] configured as Open-Drain.
1: P5.[3:0] configured as Push-Pull.
P4H: Port4 Output Mode High Nibble Bit.
0: P4.[7:4] configured as Open-Drain.
1: P4.[7:4] configured as Push-Pull.
P4L: Port4 Output Mode Low Nibble Bit.
0: P4.[3:0] configured as Open-Drain.
1: P4.[3:0] configured as Push-Pull.
Rev. 1.4
179