C8051F02X Datasheet, PDF (101/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
12. CIP-51 MICROCONTROLLER
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™
instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has
a superset of all the peripherals included with a standard 8051. Included are five 16-bit counter/timers (see descrip-
tion in Section 22), two full-duplex UARTs (see description in Section 20 and Section 21), 256 bytes of internal
RAM, 128 byte Special Function Register (SFR) address space (see Section 12.2.6), and 8/4 byte-wide I/O Ports (see
description in Section 17). The CIP-51 also includes on-chip debug hardware (see description in Section 24), and
interfaces directly with the MCUs' analog and digital subsystems providing a complete data acquisition or control-
system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional
custom peripherals and functions to extend its capability (see Figure 12.1 for a block diagram). The CIP-51 includes
the following features:
- Fully Compatible with MCS-51 Instruction Set
- 25 MIPS Peak Throughput with 25 MHz Clock
- 0 to 25 MHz Clock Frequency
- 256 Bytes of Internal RAM
- 8/4 Byte-Wide I/O Ports
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- On-chip Debug Logic
- Program and Data Memory Security
Figure 12.1. CIP-51 Block Diagram
DATA BUS
ACCUMULATOR
TMP1
TMP2
PSW
ALU
B REGISTER
STACK POINTER
SRAM
ADDRESS
REGISTER
SRAM
(256 X 8)
DATA BUS
BUFFER
D8
DATA POINTER
D8
PC INCREMENTER
SFR_ADDRESS
SFR
SFR_CONTROL
D8
BUS
SFR_WRITE_DATA
INTERFACE
SFR_READ_DATA
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
RESET
CLOCK
CONTROL
LOGIC
PIPELINE
STOP
IDLE
POWER CONTROL
REGISTER
D8
D8
MEM_ADDRESS
MEM_CONTROL
MEMORY
A16
INTERFACE ^{MEM_WRITE_DATA}
MEM_READ_DATA
D8
INTERRUPT
INTERFACE
D8
SYSTEM_IRQs
EMULATION_IRQ
Rev. 1.4
101