C8051F02X Datasheet, PDF (126/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 12.15. PCON: Power Control
R/W
SMOD0
Bit7
R/W
SSTAT0
Bit6
R/W
Reserved
Bit5
R/W
SMOD1
Bit4
R/W
SSTAT1
Bit3
R/W
Reserved
Bit2
R/W
STOP
Bit1
R/W
IDLE
Bit0
Reset Value
00000000
SFR Address:
0x87
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SMOD0: UART0 Baud Rate Doubler Enable.
This bit enables/disables the divide-by-two function of the UART0 baud rate logic for configurations
described in the UART0 section.
0: UART0 baud rate divide-by-two enabled.
1: UART0 baud rate divide-by-two disabled.
SSTAT0: UART0 Enhanced Status Mode Select.
This bit controls the access mode of the SM20-SM00 bits in register SCON0.
0: Reads/writes of SM20-SM00 access the SM20-SM00 UART0 mode setting.
1: Reads/writes of SM20-SM00 access the Framing Error (FE0), RX Overrun (RXOV0), and TX
Collision (TXCOL0) status bits.
Reserved. Read is undefined. Must write 0.
SMOD1: UART1 Baud Rate Doubler Enable.
This bit enables/disables the divide-by-two function of the UART1 baud rate logic for configurations
described in the UART1 section.
0: UART1 baud rate divide-by-two enabled.
1: UART1 baud rate divide-by-two disabled.
SSTAT1: UART1 Enhanced Status Mode Select.
This bit controls the access mode of the SM21-SM01 bits in SCON1.
0: Reads/writes of SM21-SM01 access the SM21-SM01 UART1 mode setting.
1: Reads/writes of SM21-SM01 access the Framing Error (FE1), RX Overrun (RXOV1), and TX
Collision (TXCOL1) status bits.
Reserved. Read is undefined. Must write 0.
STOP: STOP Mode Select.
Writing a ‘1’ to this bit will place the CIP-51 into STOP mode. This bit will always read ‘0’.
1: CIP-51 forced into power-down mode. (Turns off internal oscillator).
IDLE: IDLE Mode Select.
Writing a ‘1’ to this bit will place the CIP-51 into IDLE mode. This bit will always read ‘0’.
1: CIP-51 forced into idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, and all
peripherals remain active.)
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Rev. 1.4