C8051F02X Datasheet, PDF (76/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
7.2. ADC1 Modes of Operation
ADC1 has a maximum conversion speed of 500 ksps. The ADC1 conversion clock (SAR1 clock) is a divided version
of the system clock, determined by the AD1SC bits in the ADC1CF register (system clock divided by (AD1SC + 1)
for 0 ≤ AD1SC ≤ 31). The maximum ADC1 conversion clock is 6 MHz.
7.2.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC1 Start of Conver-
sion Mode bits (AD1CM2-0) in register ADC1CN. Conversions may be initiated by:
1. Writing a ‘1’ to the AD1BUSY bit of ADC1CN;
2. A Timer 3 overflow (i.e. timed continuous conversions);
3. A rising edge detected on the external ADC convert start signal, CNVSTR;
4. A Timer 2 overflow (i.e. timed continuous conversions);
5. Writing a ‘1’ to the AD0BUSY of register ADC0CN (initiate conversion of ADC1 and ADC0 with a
single software command).
During conversion, the AD1BUSY bit is set to logic 1 and restored to 0 when conversion is complete. The falling
edge of AD1BUSY triggers an interrupt (when enabled) and sets the interrupt flag in ADC1CN. Converted data is
available in the ADC1 data word, ADC1.
When a conversion is initiated by writing a ‘1’ to AD1BUSY, it is recommended to poll AD1INT to determine when
the conversion is complete. The recommended procedure is:
Step 1. Write a ‘0’ to AD1INT;
Step 2. Write a ‘1’ to AD1BUSY;
Step 3. Poll AD1INT for ‘1’;
Step 4. Process ADC1 data.
7.2.2. Tracking Modes
The AD1TM bit in register ADC1CN controls the ADC1 track-and-hold mode. In its default state, the ADC1 input is
continuously tracked, except when a conversion is in progress. When the AD1TM bit is logic 1, ADC1 operates in
low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks
(after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking
mode, ADC1 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 7.2).
Tracking can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes. Low-power
Track-and-Hold mode is also useful when AMUX or PGA settings are frequently changed, due to the settling time
requirements described in Section “7.2.3. Settling Time Requirements” on page 78.
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