C8051F02X Datasheet, PDF (78/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
7.2.3. Settling Time Requirements
When the ADC1 input configuration is changed (i.e., a different MUX or PGA selection), a minimum settling (or
tracking) time is required before an accurate conversion can be performed. This settling time is determined by the
ADC1 MUX resistance, the ADC1 sampling capacitance, any external source resistance, and the accuracy required
for the conversion. Figure 7.3 shows the equivalent ADC1 input circuit. The required ADC1 settling time for a given
settling accuracy (SA) may be approximated by Equation 7.1. Note that in low-power tracking mode, three SAR1
clocks are used for tracking at the start of every conversion. For most applications, these three SAR1 clocks will meet
the tracking requirements. See Table 7.1 for absolute minimum settling time requirements.
Equation 7.1. ADC1 Settling Time Requirements
t
=
ln


S^-2---A^{-n-}
×
R_TOTALC_SAMPLE
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required tracking time in seconds
R_TOTAL is the sum of the ADC1 MUX resistance and any external source resistance.
n is the ADC resolution in bits (8).
Figure 7.3. ADC1 Equivalent Input Circuit
MUX Select
AIN1.x
R_MUX = 5k
RC_Input= R_MUX * C_SAMPLE
C_SAMPLE = 10pF
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Rev. 1.4