C8051F02X Datasheet, PDF (186/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
18.2.3. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the mas-
ter cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies
that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a “timeout” condi-
tion. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detect-
ing the timeout condition.
18.2.4. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus is desig-
nated as free. If an SMBus device is waiting to generate a Master START, the START will be generated following a
bus free timeout.
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Rev. 1.4