C8051F02X Datasheet, PDF (244/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
22.3.1. Mode 0: 16-bit Counter/Timer with Capture
In this mode, Timer 4 operates as a 16-bit counter/timer with capture facility. A high-to-low transition on the T4EX
input pin causes the following to occur:
1. The 16-bit value in Timer 4 (TH4, TL4) is loaded into the capture registers (RCAP4H, RCAP4L).
2. The Timer 4 External Flag (EXF2) is set to ‘1’.
3. A Timer 4 interrupt is generated if enabled.
Timer 4 can use either SYSCLK, SYSCLK divided by 12, or high-to-low transitions on the T4 input pin as its clock
source when operating in Capture mode. Clearing the C/T4 bit (T4CON.1) selects the system clock as the input for
the timer (divided by one or twelve as specified by the Timer Clock Select bit T4M in CKCON). When C/T4 is set to
logic 1, a high-to-low transition at the T4 input pin increments the counter/timer register. As the 16-bit counter/timer
register increments and overflows from 0xFFFF to 0x0000, the TF4 timer overflow flag (T4CON.7) is set and an
interrupt will occur if the interrupt is enabled.
Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RL4 (T4CON.0) and the
Timer 4 Run Control bit TR4 (T4CON.2) to logic 1. The Timer 4 External Enable EXEN4 (T4CON.3) must also be
set to logic 1 to enable a capture. If EXEN4 is cleared, transitions on T4EX will be ignored.
Figure 22.25. T4 Mode 0 Block Diagram
CKCON
TTTT
4210
MMMM
SYSCLK
12
0
1
0
T4
1
Crossbar
TR4
T4EX
EXEN4
TCLK
TL4
TH4
Capture _{RCAP4L RCAP4H}
CP/RL4
C/T4
TR4
EXEN4
TCLK0
RCLK0
EXF4
TF4
Interrupt
244
Rev. 1.4