C8051F02X Datasheet, PDF (257/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
23.2.5. 8-Bit Pulse Width Modulator Mode
Each module can be used independently to generate pulse width modulated (PWM) outputs on its associated CEXn
pin. The frequency of the output is dependent on the timebase for the PCA0 counter/timer. The duty cycle of the
PWM output signal is varied using the module's PCA0CPLn capture/compare register. When the value in the low
byte of the PCA0 counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be
asserted high. When the count value in PCA0L overflows, the CEXn output will be asserted low (see Figure 23.8).
Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00, PCA0CPLn is reloaded automatically
with the value stored in the counter/timer's high byte (PCA0H) without software intervention. Setting the ECOMn
and PWMn bits in the PCA0CPMn register enables 8-Bit Pulse Width Modulator mode. The duty cycle for 8-Bit
PWM Mode is given by Equation 23.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare
registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to
PCA0CPHn sets ECOMn to ‘1’.
Equation 23.2. 8-Bit PWM Duty Cycle
DutyCycle = ⁽---2---5---6----–-----^P----^C----^A----0----^C----^P----^H-----ⁿ----⁾
256
Using Equation 23.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is 0.39%
(PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.
Figure 23.8. PCA 8-Bit PWM Mode Diagram
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn ^ENB
1
PCA0CPHn
PCA0CPMn
P ECCMT P E
WCA A AOWC
MOPP TGMC
1 MPN n n n F
6nnn
n
n
0 00x0 x
PCA0CPLn
Enable
8-bit
Comparator
match _S SET _Q
RQ
CLR
PCA Timebase
PCA0L
Overflow
CEXn _Crossbar
Port I/O
Rev. 1.4
257