C8051F02X Datasheet, PDF (79/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 7.4. ADC1CF: ADC1 Configuration Register (C8051F020/1/2/3)
R/W
AD1SC4
Bit7
R/W
AD1SC3
Bit6
R/W
AD1SC2
Bit5
R/W
AD1SC1
Bit4
R/W
AD1SC0
Bit3
R/W
R/W
R/W
Reset Value
- AMP1GN1 AMP1GN0 11111000
Bit2
Bit1
Bit0 SFR Address:
0xAB
Bits7-3:
AD1SC4-0: ADC1 SAR Conversion Clock Period Bits
SAR Conversion clock is derived from system clock by the following equation, where AD1SC refers
to the 5-bit value held in AD1SC4-0. SAR conversion clock requirements are given in Table 7.1.
AD1SC = -^S---^Y----^S---^C-----^L---^K--- – 1
CLK_SAR1
Bit2:
Bits1-0:
UNUSED. Read = 0b. Write = don’t care.
AMP1GN1-0: ADC1 Internal Amplifier Gain (PGA)
00: Gain = 0.5
01: Gain = 1
10: Gain = 2
11: Gain = 4
Figure 7.5. AMX1SL: AMUX1 Channel Select Register (C8051F020/1/2/3)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
-
-
- AMX1AD2 AMX1AD1 AMX1AD0 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xAC
Bits7-3:
Bits2-0:
UNUSED. Read = 00000b; Write = don’t care
AMX1AD2-0: AMX1 Address Bits
000-111b: ADC1 Inputs selected as follows:
000: AIN1.0 selected
001: AIN1.1 selected
010: AIN1.2 selected
011: AIN1.3 selected
100: AIN1.4 selected
101: AIN1.5 selected
110: AIN1.6 selected
111: AIN1.7 selected
Rev. 1.4
79