C8051F02X Datasheet, PDF (45/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1
5.2.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is
continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0 operates in low-
power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after
the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode,
ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 5.3). Track-
ing can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes. Low-power track-
and-hold mode is also useful when AMUX or PGA settings are frequently changed, to ensure that settling time
requirements are met (see Section “5.2.3. Settling Time Requirements” on page 46).
Figure 5.3. 12-Bit ADC Track and Conversion Example Timing
A. ADC Timing for External Trigger Source
CNVSTR
(AD0STM[1:0]=10
)
SAR Clocks
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ADC0TM=1
Low Power
or Convert
Track
ADC0TM=0 Track Or Convert
Convert
Convert
Low Power Mode
Track
B. ADC Timing for Internal Trigger Sources
Timer 2, Timer 3 Overflow;
Write '1' to AD0BUSY
(AD0STM[1:0]=00, 01, 11)
SAR Clocks
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
ADC0TM=1
Low Power
or Convert
Track
Convert
SAR Clocks
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ADC0TM=0
Track or
Convert
Convert
Low Power Mode
Track
Rev. 1.4
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