C8051F02X Datasheet, PDF (234/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
22.1. Timer 2
Timer 2 is a 16-bit counter/timer formed by the two 8-bit SFRs: TL2 (low byte) and TH2 (high byte). As with
Timers 0 and 1, Timer 2 can use either the system clock or transitions on an external input pin (T2) as its clock
source. The Counter/Timer Select bit C/T2 bit (T2CON.1) selects the clock source for Timer 2. Clearing C/T2 selects
the system clock as the input for the timer (divided by either one or twelve as specified by the Timer Clock Select bit
T2M in CKCON). When C/T2 is set to 1, high-to-low transitions at the T2 input pin increment the counter/timer reg-
ister. (Refer to Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder” on page 163 for information
on selecting and configuring external I/O pins for digital peripherals.) Timer 2 can also be used to start an ADC Data
Conversion.
Timer 2 offers capabilities not found in Timer 0 and Timer 1. It operates in one of three modes: 16-bit Counter/Timer
with Capture, 16-bit Counter/Timer with Auto-Reload or Baud Rate Generator Mode. Timer 2's operating mode is
selected by setting configuration bits in the Timer 2 Control register (T2CON). Below is a summary of the Timer 2
operating modes and the T2CON bits used to configure the counter/timer. Detailed descriptions of each mode follow.
RCLK0
0
0
0
1
1
X
TCLK0
0
0
1
0
1
X
CP/RL2
1
0
X
X
X
X
TR2 Mode
1 16-bit Counter/Timer with Capture
1 16-bit Counter/Timer with Auto-Reload
1 Baud Rate Generator for UART0
1 Baud Rate Generator for UART0
1 Baud Rate Generator for UART0
0 Off
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Rev. 1.4