C8051F02X Datasheet, PDF (83/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
8. DACS, 12-BIT VOLTAGE MODE
Each C8051F020/1/2/3 device includes two on-chip 12-bit voltage-mode Digital-to-Analog Converters (DACs).
Each DAC has an output swing of 0V to (VREF-1LSB) for a corresponding input code range of 0x000 to 0xFFF. The
DACs may be enabled/disabled via their corresponding control registers, DAC0CN and DAC1CN. While disabled,
the DAC output is maintained in a high-impedance state, and the DAC supply current falls to 1 µA or less. The volt-
age reference for each DAC is supplied at the VREFD pin (C8051F020/2 devices) or the VREF pin (C8051F021/3
devices). Note that the VREF pin on C8051F021/3 devices may be driven by the internal voltage reference or an
external source. If the internal voltage reference is used it must be enabled in order for the DAC outputs to be valid.
See Section “9. VOLTAGE REFERENCE (C8051F020/2)” on page 91 or Section “10. VOLTAGE REFER-
ENCE (C8051F021/3)” on page 93 for more information on configuring the voltage reference for the DACs.
8.1. DAC Output Scheduling
Each DAC features a flexible output update mechanism which allows for seamless full-scale changes and supports
jitter-free updates for waveform generation. The following examples are written in terms of DAC0, but DAC1 opera-
tion is identical. Note that reads from DAC0L return pre-latch data, meaning the value read is the same as the last
value written to this register, not the value at the DAC0L latch. Reads from DAC0H always return the value at the
DAC0H latch.
Figure 8.1. DAC Functional Block Diagram
DAC0EN
DAC0MD1
DAC0MD0
DAC0DF2
DAC0DF1
DAC0DF0
8
8
8
8
REF
12
DAC0
AV+
AGND
DAC0
DAC1EN
DAC1MD1
DAC1MD0
DAC1DF2
DAC1DF1
DAC1DF0
8
8
8
8
REF
12
DAC1
Rev. 1.4
AV+
AGND
DAC1
83