C8051F02X Datasheet, PDF (226/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 22.1. CKCON: Clock Control Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
T4M
T2M
T1M
T0M Reserved Reserved Reserved 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0x8E
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bits2-0:
UNUSED. Read = 0b, Write = don’t care.
T4M: Timer 4 Clock Select.
This bit controls the division of the system clock supplied to Timer 4. This bit is ignored when the
timer is in baud rate generator mode or counter mode (i.e. C/T4 = 1).
0: Timer 4 uses the system clock divided by 12.
1: Timer 4 uses the system clock.
T2M: Timer 2 Clock Select.
This bit controls the division of the system clock supplied to Timer 2. This bit is ignored when the
timer is in baud rate generator mode or counter mode (i.e. C/T2 = 1).
0: Timer 2 uses the system clock divided by 12.
1: Timer 2 uses the system clock.
T1M: Timer 1 Clock Select.
This bit controls the division of the system clock supplied to Timer 1.
0: Timer 1 uses the system clock divided by 12.
1: Timer 1 uses the system clock.
T0M: Timer 0 Clock Select.
This bit controls the division of the system clock supplied to Counter/Timer 0.
0: Counter/Timer uses the system clock divided by 12.
1: Counter/Timer uses the system clock.
Reserved. Read = 000b, Must Write = 000.
226
Rev. 1.4