C8051F02X Datasheet, PDF (230/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
22.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
Timer 0 and Timer 1 behave differently in Mode 3. Timer 0 is configured as two separate 8-bit counter/timers held in
TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD:
TR0, C/T0, GATE0 and TF0. It can use either the system clock or an external input signal as its timebase. The timer
in the TH0 register is restricted to a timer function sourced by the system clock. TH0 is enabled using the Timer 1 run
control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt.
Timer 1 is inactive in Mode 3, so with Timer 0 in Mode 3, Timer 1 can be turned off and on by switching it into and
out of its Mode 3. When Timer 0 is in Mode 3, Timer 1 can be operated in Modes 0, 1 or 2, but cannot be clocked by
external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1 overflow can be used to gener-
ate the baud clock for UART0 and/or UART1. Refer to Section “20. UART0” on page 205 and Section
“21. UART1” on page 215 for information on configuring Timer 1 for baud rate generation.
Figure 22.4. T0 Mode 3 (Two 8-bit Timers) Block Diagram
CKCON
TTTT
4210
MMMM
TMOD
GCT TGCT T
A / 11A / 00
T T MM T T MM
E1 1 0E0 1 0
1
0
12
SYSCLK
T0
Crossbar
/INT0
0
1
0
1
TR0
TR1
TH0
(8 bits)
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TL0
(8 bits)
Interrupt
Interrupt
GATE0
230
Rev. 1.4