C8051F02X Datasheet, PDF (217/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
21.1.2. Mode 1: 8-Bit UART, Variable Baud Rate
Mode 1 provides standard asynchronous, full duplex communication using a total of 10 bits per data byte: one start
bit, eight data bits (LSB first), and one stop bit. Data are transmitted from the TX1 pin and received at the RX1 pin.
On receive, the eight data bits are stored in SBUF1 and the stop bit goes into RB81 (SCON1.2).
Data transmission begins when an instruction writes a data byte to the SBUF1 register. The TI1 Transmit Interrupt
Flag (SCON1.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin
any time after the REN1 Receive Enable bit (SCON1.4) is set to logic 1. After the stop bit is received, the data byte
will be loaded into the SBUF1 receive register if the following conditions are met: RI1 must be logic 0, and if SM21
is logic 1, the stop bit must be logic 1.
If these conditions are met, the eight bits of data are stored in SBUF1, the stop bit is stored in RB81 and the RI1 flag
is set. If these conditions are not met, SBUF1 and RB81 will not be loaded and the RI1 flag will not be set. An inter-
rupt will occur if enabled when either TI1 or RI1 is set.
Figure 21.4. UART1 Mode 1 Timing Diagram
MARK
SPACE
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
STOP
BIT
BIT TIMES
BIT SAMPLING
The baud rate generated in Mode 1 is a function of timer overflow, shown in Equation 21.1 and Equation 21.2.
UART1 can use Timer 1 operating in 8-Bit Auto-Reload Mode, or Timer 4 operating in Baud Rate Generator Mode to
generate the baud rate (note that the TX and RX clocks are selected separately). On each timer overflow event (a roll-
over from all ones - (0xFF for Timer 1, 0xFFFF for Timer 4) - to zero) a clock is sent to the baud rate logic.
Timer 4 is selected as TX and/or RX baud clock source by setting the TCLK1 (T4CON.4) and/or RCLK1 (T4CON.5)
bits, respectively (see Section “22. TIMERS” on page 225 for complete timer configuration details). When either
TCLK1 or RCLK1 is set to logic 1, Timer 4 is forced into Baud Rate Generator Mode, with SYSCLK / 2 as its clock
source. If TCLK1 and/or RCLK1 is logic 0, Timer 1 acts as the baud clock source for the TX and/or RX circuits,
respectively.
The Mode 1 baud rate equations are shown below, where T1M is the Timer 1 Clock Select bit (register CKCON),
TH1 is the 8-bit reload register for Timer 1, SMOD1 is the UART1 baud rate doubler (register PCON), and
[RCAP4H , RCAP4L] is the 16-bit reload register for Timer 4.
Equation 21.1. Mode 1 Baud Rate using Timer 1
BaudRate
=


-2---^S--^M-3---2^O----^D---¹-_
×


S_----Y_----S_---C_--(--L_-2---5K_---6--×_{--–---1--T-2--H--}⁽_-^T_--1-¹_--)-^M_----^–_----¹_---⁾_-⁾_
Equation 21.2. Mode 1 Baud Rate using Timer 4
BaudRate = _[---3---2----_×-----₍---6---5---5---3---6----–----^S-[---_RY---^S-_C---^C-_A---^L-_P---^K-4---_H----,---_R----_C----_A----_P----4----_L----]--₎---_]
Rev. 1.4
217