C8051F02X Datasheet, PDF (22/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F020 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compati-
ble with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The core has all the peripherals included with a standard 8052, including five 16-bit counter/timers, two full-
duplex UARTs, 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and 8/4 byte-
wide I/O Ports.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to exe-
cute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in
one or two system clock cycles, with only four instructions taking more than four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each
execution time.
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
Number of Instructions
26
50
5
14
7
3
1
2
1
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.5 shows a com-
parison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks.
Figure 1.5. Comparison of Peak MCU Execution Speeds
25
20
15
10
5
Silicon Labs Microchip Philips ADuC812
CIP-51 PIC17C75x 80C51
8051
(25MHz clk) (33MHz clk) (33MHz clk) (16MHz clk)
22
Rev. 1.4