C8051F02X Datasheet, PDF (17/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
1. SYSTEM OVERVIEW
The C8051F020/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital I/O pins
(C8051F020/2) or 32 digital I/O pins (C8051F021/3). Highlighted features are listed below; refer to Table 1.1 for
specific product feature selection.
• High-Speed pipelined 8051-compatible CIP-51 microcontroller core (up to 25 MIPS)
• In-system, full-speed, non-intrusive debug interface (on-chip)
• True 12-bit (C8051F020/1) or 10-bit (C8051F022/3) 100 ksps 8-channel ADC with PGA and analog multiplexer
• True 8-bit ADC 500 ksps 8-channel ADC with PGA and analog multiplexer
• Two 12-bit DACs with programmable update scheduling
• 64k bytes of in-system programmable FLASH memory
• 4352 (4096 + 256) bytes of on-chip RAM
• External Data Memory Interface with 64k byte address space
• SPI, SMBus/I²C, and (2) UART serial interfaces implemented in hardware
• Five general purpose 16-bit Timers
• Programmable Counter/Timer Array with five capture/compare modules
• On-chip Watchdog Timer, VDD Monitor, and Temperature Sensor
With on-chip VDD monitor, Watchdog Timer, and clock oscillator, the C8051F020/1/2/3 devices are truly stand-
alone System-on-a-Chip solutions. All analog and digital peripherals are enabled/disabled and configured by user
firmware. The FLASH memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also
allowing field upgrades of the 8051 firmware.
On-board JTAG debug circuitry allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging
using the production MCU installed in the final application. This debug system supports inspection and modification
of memory and registers, setting breakpoints, watchpoints, single stepping, run and halt commands. All analog and
digital peripherals are fully functional while debugging using JTAG.
Each MCU is specified for 2.7 V-to-3.6 V operation over the industrial temperature range (-45° C to +85° C). The
Port I/Os, /RST, and JTAG pins are tolerant for input signals up to 5 V. The C8051F020/2 are available in a 100-pin
TQFP package (see block diagrams in Figure 1.1 and Figure 1.3). The C8051F021/3 are available in a 64-pin TQFP
package (see block diagrams in Figure 1.2 and Figure 1.4).
Table 1.1. Product Selection Guide
C8051F020 25 64k 4352 3 3 3 2 5 3 64 8 - 8 3 3 12 2 2 100TQFP
C8051F021 25 64k 4352 3 3 3 2 5 3 32 8 - 8 3 3 12 2 2 64TQFP
C8051F022 25 64k 4352 3 3 3 2 5 3 64 - 8 8 3 3 12 2 2 100TQFP
C8051F023 25 64k 4352 3 3 3 2 5 3 32 - 8 8 3 3 12 2 2 64TQFP
Rev. 1.4
17