C8051F02X Datasheet, PDF (215/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
21. UART1
UART1 is an enhanced serial port with frame error detection and address recognition hardware. UART1 may operate
in full-duplex asynchronous or half-duplex synchronous modes, and mutiproccessor communication is fully sup-
ported. Receive data is buffered in a holding register, allowing UART1 to start reception of a second incoming data
byte before software has finished reading the previous data byte. A Receive Overrun bit indicates when new received
data is latched into the receive buffer before the previous received byte is read.
UART1 is accessed via its associated SFRs, Serial Control (SCON1) and Serial Data Buffer (SBUF1). The single
SBUF1 location provides access to both transmit and receive registers. Reads access the Receive register and writes
access the Transmit register automatically.
UART1 may be operated in polled or interrupt mode. UART1 has two sources of interrupts: a Transmit Interrupt flag,
TI1 (SCON1.1) set when transmission of a data byte is complete, and a Receive Interrupt flag, RI1 (SCON1.0) set
when reception of a data byte is complete. UART1 interrupt flags are not cleared by hardware when the CPU vectors
to the interrupt service routine; they must be cleared manually by software. This allows software to determine the
cause of the UART1 interrupt (transmit complete or receive complete).
Figure 21.1. UART1 Block Diagram
SFR Bus
Write to
SBUF
TB8
SET
DQ
CLR
SBUF
(Transmit Shift)
Zero Detector
TX
Crossbar
UART
Baud Rate
Generation
Logic
Stop Bit
Gen.
Start
Tx Clock
Shift
Tx Control
Tx IRQ
Data
Send
SCON
TI
SSSRTRTR
MMME B B I I
0 1 2N8 8
RI
Rx Clock
Start
EN
Rx IRQ
Load
SBUF
Rx Control
Address
Match
Shift
0x1FF
Serial Port
(UART0/1)
Interrupt
Port I/O
Frame Error
Detection
Input Shift Register
(9 bits)
Load SBUF
RB8
SBUF
(Receive Latch)
Match Detect
Read
SBUF
SADDR
SADEN
SFR Bus
RX
Crossbar
Rev. 1.4
215