C8051F02X Datasheet, PDF (14/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 21.7. UART Multi-Processor Mode Interconnect Diagram .......................................220
Table 21.2. Oscillator Frequencies for Standard Baud Rates...............................................222
Figure 21.8. SCON1: UART1 Control Register....................................................................223
Figure 21.9. SBUF1: UART1 Data Buffer Register..............................................................224
Figure 21.10. SADDR1: UART1 Slave Address Register ....................................................224
Figure 21.11. SADEN1: UART1 Slave Address Enable Register ........................................224
22. TIMERS................................................................................................................................225
Figure 22.1. CKCON: Clock Control Register......................................................................226
Figure 22.2. T0 Mode 0 Block Diagram................................................................................228
Figure 22.3. T0 Mode 2 (8-bit Auto-Reload) Block Diagram...............................................229
Figure 22.4. T0 Mode 3 (Two 8-bit Timers) Block Diagram................................................230
Figure 22.5. TCON: Timer Control Register.........................................................................231
Figure 22.6. TMOD: Timer Mode Register...........................................................................232
Figure 22.7. TL0: Timer 0 Low Byte ....................................................................................233
Figure 22.8. TL1: Timer 1 Low Byte ....................................................................................233
Figure 22.9. TH0 Timer 0 High Byte ....................................................................................233
Figure 22.10. TH1: Timer 1 High Byte .................................................................................233
Figure 22.11. T2 Mode 0 Block Diagram..............................................................................235
Figure 22.12. T2 Mode 1 Block Diagram..............................................................................236
Figure 22.13. T2 Mode 2 Block Diagram..............................................................................237
Figure 22.14. T2CON: Timer 2 Control Register..................................................................238
Figure 22.15. RCAP2L: Timer 2 Capture Register Low Byte ..............................................239
Figure 22.16. RCAP2H: Timer 2 Capture Register High Byte .............................................239
Figure 22.17. TL2: Timer 2 Low Byte ..................................................................................239
Figure 22.18. TH2 Timer 2 High Byte ..................................................................................239
Figure 22.19. Timer 3 Block Diagram...................................................................................240
Figure 22.20. TMR3CN: Timer 3 Control Register ..............................................................241
Figure 22.21. TMR3RLL: Timer 3 Reload Register Low Byte ............................................241
Figure 22.22. TMR3RLH: Timer 3 Reload Register High Byte ...........................................242
Figure 22.23. TMR3L: Timer 3 Low Byte ............................................................................242
Figure 22.24. TMR3H: Timer 3 High Byte ...........................................................................242
Figure 22.25. T4 Mode 0 Block Diagram..............................................................................244
Figure 22.26. T4 Mode 1 Block Diagram..............................................................................245
Figure 22.27. T4 Mode 2 Block Diagram..............................................................................246
Figure 22.28. T4CON: Timer 4 Control Register..................................................................247
Figure 22.29. RCAP4L: Timer 4 Capture Register Low Byte ..............................................248
Figure 22.30. RCAP4H: Timer 4 Capture Register High Byte .............................................248
Figure 22.31. TL4: Timer 4 Low Byte ..................................................................................248
Figure 22.32. TH4 Timer 4 High Byte ..................................................................................248
23. PROGRAMMABLE COUNTER ARRAY .......................................................................249
Figure 23.1. PCA Block Diagram..........................................................................................249
Figure 23.2. PCA Counter/Timer Block Diagram .................................................................250
Table 23.1. PCA Timebase Input Options............................................................................250
Figure 23.3. PCA Interrupt Block Diagram...........................................................................252
Table 23.2. PCA0CPM Register Settings for PCA Capture/Compare Modules..................252
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Rev. 1.4