C8051F02X Datasheet, PDF (128/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
13.1. Power-on Reset
The C8051F020/1/2/3 family incorporates a power supply monitor that holds the MCU in the reset state until VDD
rises above the V_RST level during power-up. See Figure 13.2 for timing diagram, and refer to Table 13.1 for the Elec-
trical Characteristics of the power supply monitor circuit. The /RST pin is asserted low until the end of the 100 ms
VDD Monitor timeout in order to allow the VDD supply to stabilize.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other reset flags
in the RSTSRC Register are indeterminate. PORSF is cleared by all other resets. Since all resets cause program exe-
cution to begin at the same location (0x0000), software can read the PORSF flag to determine if a power-up was the
cause of reset. The contents of internal data memory should be assumed to be undefined after a power-on reset.
The VDD monitor function is enabled by tying the MONEN pin directly to VDD. This is the recommended
configuration for the MONEN pin.
.
Figure 13.2. Reset Timing
2.70
2.55
2.0
1.0
V_RST
Logic HIGH
/RST
Logic LOW
100ms
Power-On Reset
t
100ms
VDD Monitor Reset
13.2. Power-fail Reset
When a power-down transition or power irregularity causes VDD to drop below V_RST, the power supply monitor will
drive the /RST pin low and return the CIP-51 to the reset state. When VDD returns to a level above VRST, the CIP-51
will leave the reset state in the same manner as that for the power-on reset (see Figure 13.2). Note that even though
internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped
below the level required for data retention. If the PORSF flag is set to logic 1, the data may no longer be valid.
128
Rev. 1.4