C8051F02X Datasheet, PDF (235/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
22.1.1. Mode 0: 16-bit Counter/Timer with Capture
In this mode, Timer 2 operates as a 16-bit counter/timer with capture facility. A high-to-low transition on the T2EX
input pin causes the following to occur:
1. The 16-bit value in Timer 2 (TH2, TL2) is loaded into the capture registers (RCAP2H, RCAP2L).
2. The Timer 2 External Flag (EXF2) is set to ‘1’.
3. A Timer 2 interrupt is generated if enabled.
Timer 2 can use either SYSCLK, SYSCLK divided by 12, or high-to-low transitions on the T2 input pin as its clock
source when operating in Capture mode. Clearing the C/T2 bit (T2CON.1) selects the system clock as the input for
the timer (divided by one or twelve as specified by the Timer Clock Select bit T2M in CKCON). When C/T2 is set to
logic 1, a high-to-low transition at the T2 input pin increments the counter/timer register. As the 16-bit counter/timer
register increments and overflows from 0xFFFF to 0x0000, the TF2 timer overflow flag (T2CON.7) is set and an
interrupt will occur if the interrupt is enabled.
Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RL2 (T2CON.0) and the
Timer 2 Run Control bit TR2 (T2CON.2) to logic 1. The Timer 2 External Enable EXEN2 (T2CON.3) must also be
set to logic 1 to enable a capture. If EXEN2 is cleared, transitions on T2EX will be ignored.
Figure 22.11. T2 Mode 0 Block Diagram
CKCON
TTTT
4210
MMMM
SYSCLK
12
0
1
0
T2
1
Crossbar
TR2
T2EX
EXEN2
TCLK
TL2
TH2
Capture _{RCAP2L RCAP2H}
CP/RL2
C/T2
TR2
EXEN2
TCLK0
RCLK0
EXF2
TF2
Interrupt
Rev. 1.4
235