C8051F02X Datasheet, PDF (140/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Write/Erase timing is automatically controlled by hardware. Note that code execution in the 8051 is stalled while the
FLASH is being programmed or erased. Interrupts that are posted during a FLASH write or erase operation are held
pending until the FLASH operation has completed, at which time they are serviced by the CPU in priority order.
Table 15.1. FLASH Electrical Characteristics
VDD = 2.7V to 3.6V; T_a = -40°C to +85°C
PARAMETER
CONDITIONS
MIN TYP
Endurance
20k
100k
Erase Cycle Time
10
12
Write Cycle Time
40
50
MAX
14
60
UNITS
Erase/Write
ms
µs
15.2. Non-volatile Data Storage
The FLASH memory can be used for non-volatile data storage as well as program code. This allows data such as cal-
ibration coefficients to be calculated and stored at run time. Data is written using the MOVX write instruction (as
described in the previous section) and read using the MOVC read instruction.
An additional 128-byte sector of FLASH memory is included for non-volatile data storage. Its smaller sector size
makes it particularly well suited as general purpose, non-volatile scratchpad memory. Even though FLASH memory
can be written a single byte at a time, an entire sector must be erased first. In order to change a single byte of a multi-
byte data set, the data must be moved to temporary storage. The 128-byte sector-size facilitates updating data without
wasting program memory or RAM space. The 128-byte sector is double-mapped over the 64k byte FLASH memory;
its address ranges from 0x00 to 0x7F (see Figure 15.1). To access this 128-byte sector, the SFLE bit in PSCTL must
be set to logic 1. Code execution from this 128-byte scratchpad sector is not permitted.
15.3. Security Options
The CIP-51 provides security options to protect the FLASH memory from inadvertent modification by software as
well as prevent the viewing of proprietary program code and constants. The Program Store Write Enable (PSCTL.0)
and the Program Store Erase Enable (PSCTL.1) bits protect the FLASH memory from accidental modification by
software. These bits must be explicitly set to logic 1 before software can modify the FLASH memory. Additional
security features prevent proprietary program code and data constants from being read or altered across the JTAG
interface or by software running on the system controller.
A set of security lock bytes stored at 0xFDFE and 0xFDFF protect the FLASH program memory from being read or
altered across the JTAG interface. Each bit in a security lock-byte protects one 8k-byte block of memory. Clearing a
bit to logic 0 in a Read Lock Byte prevents the corresponding block of FLASH memory from being read across the
JTAG interface. Clearing a bit in the Write/Erase Lock Byte protects the block from JTAG erasures and/or writes. The
128-byte scratchpad sector is locked only when all other sectors are locked.
The Read Lock Byte is at location 0xFDFF. The Write/Erase Lock Byte is located at 0xFDFE. Figure 15.1 shows the
location and bit definitions of the security bytes. The 512-byte sector containing the lock bytes can be written to, but
not erased by software. An attempted read of a read-locked byte returns undefined data. Debugging code in a read-
locked sector is not possible through the JTAG port.
140
Rev. 1.4