C8051F02X Datasheet, PDF (210/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
20.2. Multiprocessor Communications
Modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors
by special use of the ninth data bit and the built-in UART0 address recognition hardware. A master processor begins
a transfer with an address byte to select one or more target slave devices. An address byte differs from a data byte in
that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
The UART0 address is configured via two SFRs: SADDR0 (Serial Address) and SADEN0 (Serial Address Enable).
SADEN0 sets the bit mask for the address held in SADDR0: bits set to logic 1 in SADEN0 correspond to bits in
SADDR0 that are checked against the received address byte; bits set to logic 0 in SADEN0 correspond to “don’t
care” bits in SADDR0.
Example 1
SADDR0 = 00110101
SADEN0 = 00001111
UART0 Address = xxxx0101
Example 2
SADDR0 = 00110101
SADEN0 = 11110011
UART0 Address = 0011xx01
Example 3
SADDR0 = 00110101
SADEN0 = 11000000
UART0 Address = 00xxxxxx
Setting the SM20 bit (SCON0.5) configures UART0 such that when a stop bit is received, UART0 will generate an
interrupt only if the ninth bit is logic 1 (RB80 = 1) and the received data byte matches the UART0 slave address. Fol-
lowing the received address interrupt, the slave should clear its SM20 bit to enable interrupts on the reception of the
following data byte(s). Once the entire message is received, the addressed slave should reset its SM20 bit to ignore all
transmissions until it receives the next address byte. While SM20 is logic 1, UART0 ignores all bytes that do not
match the UART0 address and include a ninth bit that is logic 1.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves,
thereby enabling "broadcast" transmissions to more than one slave simultaneously. The broadcast address is the logi-
cal OR of registers SADDR0 and SADEN0, and ‘0’s of the result are treated as “don’t cares”. Typically a broadcast
address of 0xFF (hexadecimal) is acknowledged by all slaves, assuming “don’t care” bits as ‘1’s. The master proces-
sor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is
temporarily reversed to enable half-duplex transmission between the original master and slave(s).
Figure 20.7. UART Multi-Processor Mode Interconnect Diagram
Master
Device
RX
TX
Slave
Device
RX
TX
Slave
Device
RX
TX
Slave
Device
+5V
RX
TX
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Rev. 1.4