C8051F02X Datasheet, PDF (174/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
Figure 17.12. P1: Port1 Data Register
R/W
P1.7
Bit7
R/W
P1.6
Bit6
R/W
P1.5
Bit5
R/W
P1.4
Bit4
R/W
P1.3
Bit3
R/W
P1.2
Bit2
R/W
P1.1
Bit1
R/W
Reset Value
P1.0 11111111
Bit0 SFR Address:
(bit addressable) 0x90
Bits7-0:
P1.[7:0]: Port1 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P1MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).
0: P1.n pin is logic low.
1: P1.n pin is logic high.
Notes:
1.
2.
P1.[7:0] can be configured as inputs to ADC1 as AIN1.[7:0], in which case they are ‘skipped’ by the
Crossbar assignment process and their digital input paths are disabled, depending on P1MDIN (See
Figure 17.13). Note that in analog mode, the output mode of the pin is determined by the Port 1 latch
and P1MDOUT (Figure 17.14). See Section “7. ADC1 (8-Bit ADC)” on page 75 for more informa-
tion about ADC1.
P1.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-multiplexed
mode). See Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM”
on page 145 for more information about the External Memory Interface.
Figure 17.13. P1MDIN: Port1 Input Mode Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xBD
Bits7-0:
P1MDIN.[7:0]: Port 1 Input Mode Bits.
0: Port Pin is configured in Analog Input mode. The digital input path is disabled (a read from the
Port bit will always return ‘0’). The weak pull-up on the pin is disabled.
1: Port Pin is configured in Digital Input mode. A read from the Port bit will return the logic level at
the Pin. The state of the weak pull-up is determined by the WEAKPUD bit (XBR2.7, see
Figure 17.9).
174
Rev. 1.4