C8051F02X Datasheet, PDF (161/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
17. PORT INPUT/OUTPUT
The C8051F020/1/2/3 are fully integrated mixed-signal System on a Chip MCUs with 64 digital I/O pins
(C8051F020/2) or 32 digital I/O pins (C8051F021/3), organized as 8-bit Ports. The lower ports: P0, P1, P2, and P3,
are both bit- and byte-addressable through their corresponding Port Data registers. The upper ports: P4, P5, P6, and
P7 are byte-addressable. All Port pins are 5 V-tolerant, and all support configurable Open-Drain or Push-Pull output
modes and weak pull-ups. A block diagram of the Port I/O cell is shown in Figure 17.1. Complete Electrical Specifi-
cations for the Port I/O pins are given in Table 16.1.
Figure 17.1. Port I/O Cell Block Diagram
/WEAK-PULLUP
PUSH-PULL
/PORT-OUTENABLE
PORT-OUTPUT
VDD
VDD
(WEAK)
PORT
PAD
ANALOG INPUT
PORT-INPUT
Analog Select
(Port 1 Only)
DGND
Table 17.1. Port I/O DC Electrical Characteristics
VDD = 2.7 V to 3.6 V, -40°C to +85°C unless otherwise specified.
PARAMETER
CONDITIONS
Output High Voltage (V_OH) I_OH = -10 µA, Port I/O Push-Pull
I_OH = -3 mA, Port I/O Push-Pull
I_OH = -10 mA, Port I/O Push-Pull
Output Low Voltage (V_OL) I_OL = 10 µA
I_OL = 8.5 mA
I_OL = 25 mA
Input High Voltage (VIH)
Input Low Voltage (VIL)
MIN
TYP
VDD - 0.1
VDD - 0.7
VDD - 0.8
1.0
0.7 x VDD
Input Leakage Current
DGND < Port Pin < VDD, Pin Tri-state
Weak Pull-up Off
Weak Pull-up On
10
Input Capacitance
5
MAX
0.1
0.6
0.3 x
VDD
±1
UNITS
V
V
V
V
µA
pF
Rev. 1.4
161