C8051F02X Datasheet, PDF (254/272 Pages) Silicon Laboratories – 8K ISP FLASH MCU Family

C8051F020/1/2/3
23.2.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA0 counter/timer is compared to the module's 16-bit capture/compare register
(PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic
1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by
hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Setting the ECOMn
and MATn bits in the PCA0CPMn register enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare
registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to
PCA0CPHn sets ECOMn to ‘1’.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn ^ENB
1
Figure 23.5. PCA Software Timer Mode Diagram
PCA0CPMn
P ECCMT P E
WCA A AOWC
MOPP TGMC
1 MPN n n n F
6nnn
n
n
x 00 00x
Enable
PCA0CPLn PCA0CPHn
16-bit Comparator
Match
PCA Interrupt
PCA0CN
CC CCCCC
FR CCCCC
FFFFF
43210
0
1
PCA
Timebase
PCA0L
PCA0H
254
Rev. 1.4